1. Field of the Invention
This invention relates to a vertical channel FET (field effect transistor) formed on an insulating film using a cladding technique, and more particularly to a vertical channel FET which is easy to manufacture in fine structure, and also to a process of manufacturing such vertical channel FET and a semiconductor memory which employs such vertical channel FET and has improved electric characteristics.
2. Description of the Prior Art
An FET which is commonly used as a device for an integrated circuit is constructed such that a channel extends in parallel to a front surface of a substrate and a sum total of areas of the source, drain and channel makes an occupied area of the FET device. Accordingly, fine structure is difficult with such FET.
An exemplary one of such FETs is disclosed, for example, in Japanese Patent Laid-Open Application No. 63-40376 and shown in FIGS. 1 and 2. Referring to FIGS. 1 and 2, a gate electrode 2 is formed on an insulator 1, and a gate insulator 3 is formed on an outer circumference of the gate electrode 2. A source (or drain) 5 of an N-type semiconductor, a P-type semiconductor 6 and a drain (or source) 7 of an N-type semiconductor are formed in this order from above such that they surround the gate insulator 3, and an N-type channel 4 is formed in the semiconductor 6 adjacent the gate insulator 3 by controlling a voltage to the gate electrode 2.
Since the channel 4 is formed on the entire outer circumference of the gate electrode 2 in a vertical direction as apparently seen from FIG. 1, such transistors have a high mutual conductance.
In such conventional vertical FET as described above, either one of the source and drain is positioned at the bottom, and accordingly, when a large number of vertical channel FETs are to be formed on an integrated circuit and wired to each other, either one of the source and drain of each of such vertical channel FETs which is positioned at the bottom must be led out to a front surface of the semiconductor device. Accordingly, such conventional vertical FET is restricted in improvement in fine structure.
Further, parasitic capacities of the source and drain with respect to a substrate are significantly high, and also a substrate biasing effect is high.
Besides, it is difficult to sufficiently reduce the thickness of a portion of semiconductor on which a channel is to be formed in a depthwise direction of the channel.